1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to those providing a faster column-related operation.
2. Description of the Background Art
In recent years, there has been a demand for increasing data in capacity and also communicating the data rapidly and a multi input and output and multibank, logic embedded dynamic random access memory (eDRAM) has accordingly been generally used.
FIG. 24 represents a relationship between a memory bank BK and column select lines CSL_ODD less than 1:0 greater than  and CSL_EVEN less than 1:0 greater than . Note that hereinafter for a plurality of bits  less than Z:0 greater than , 0 to Z are applied, wherein Z represents a natural number.
Memory bank BK includes a row decoder 1004, a sense amplifier bands SAG(0)-SAG(4) (hereinafter generally referred to as a sense amplifier band SAG), and memory blocks MBL(0)-MBL(3) (hereinafter generally referred to as a memory block MBL). Each memory block MBL is arranged between sense amplifier bands SAGs. When a signal is input from column select lines CSL_ODD less than 1:0 greater than  and CSL_EVEN less than 1:0 greater than  to each sense amplifier band SAG a signal is input to each sense amplifier band SAG via a driver DRI. Each sense amplifier band SAG includes a plurality of bit line select circuits BSLs and it is activated by any signal input from column select lines CSL_ODD less than 1:0 greater than  and CSL_EVEN less than 1:0 greater than  to electrically connect each bit line pair and input/output line pairs IO(0), /IO(0) to IO(m), /IO(m) respectively (hereinafter generally referred to as an input/output line pair IO, /IO) to read or write data, wherein m represents a natural number. Each input/output line pair IO and /IO is arranged orthogonal to each memory block MBL.
A description will now be provided of a sense amplifier block 1100 including bit line select circuit BSLs of their respective sense amplifier bands SAG(0) and SAG(1) at the bottom. The other sense amplifier blocks are similarly configured and thus will not be described specifically.
FIG. 25 shows a circuit configuration of sense amplifier block 1100.
Each sense amplifier band SAG has a circuit configuration in a shared SA system and sense amplifier block 1100 includes an input/output line pair /IO(m) and IO(m), bit line pairs BL0, /BL0 to /BL3, BL3, hereinafter generally referred to as a bit line pair BL and /BL, a sense amplifier circuit S/A, and column select lines CSL_ODD1, CSL_ODD0, CSL_EVEN1 and CSL_EVEN0.
Column select lines CSL_ODD1 and CSL_ODD0 connect with bit line select circuits BSL0, BSL1, respectively. Each bit line pair BL, /BL is connected to each bit line select circuit BSL via sense amplifier circuit S/A. Furthermore, bit line select circuit BSL0 and BSL1 are connected to input/output line pair IO(m), /IO(m) respectively.
FIG. 26 shows a circuit configuration of bit line select circuits BSL0 and BSL1.
Bit line select circuits BSL0 and BSL1 include N channel MOS transistors NT1, NT2, respectively, operating as a gate circuit, and when bit line select circuit BSL0 is activated by a signal on column select line CSL_ODD1 and n channel MOS transistor NT1 turns on, input/output line pair IO(m), /IO(m) and bit line pair BL3, /BL3 are electrically coupled together. When bit line select circuit BSL1 is activated by a signal on column select line CSL_ODD0 and N channel MOS transistor NT2 turns on, input/output line pair IO(m), /IO(m) and bit line pair BL1, /BL1 are electrically coupled together. Thus one of the signals on column select lines CSL_ODD1 and CSL_ODD0 input activates each bit line select circuit BSL connected to the respective signal lines and data is thus read or written.
Reference will again be made to FIG. 24 to consider an example with a plurality of memory banks BKs.
Memory bank BK shares column select lines CSL_EVEN less than 1:0 greater than  and CSL_ODD less than 1:0 greater than . Column select line CSL_EVEN less than 1:0 greater than , connected to odd-numbered sense amplifier bands SAGs, has two drivers DRIs connected for a unit memory bank BK, and column select line CSL_ODD less than 1:0 greater than , connected to even-numbered sense amplifier bands SAGs, has three drivers DRIs connected per a unit memory bank BK. This results in a ratio in load of two to three and column select line CSL_ODD less than 1:0 greater than  is larger in load than column select line CSL_EVEN less than 1:0 greater than , resulting in a delayed timing of a signal to be transmitted.
FIG. 27 is timing plots in a write operation.
As shown in FIG. 27, in the write operation input/output line pair IO and /IO is driven in response to data to high and low levels, respectively. During that period, bit line pair BL, /BL must be selected in response to column select lines CSL_EVEN less than 1:0 greater than  and CSL_ODD less than 1:0 greater than  to write data, although if there is a difference in tiling between column select lines CSL_EVEN less than 1:0 greater than  and CSL_ODD less than 1:0 greater than  that is associated with a difference in load, input/output line pair IO, /IO must be driven continuously throughout a period satisfying the difference in timing of the two. Thus a column cycle (tC) cannot be reduced and rapid column-related operation cannot be achieved.
FIG. 28 shows another configuration different from that of FIG. 24, showing a memory bank configuration effecting a column select operation in response to a predecoded signal.
FIG. 28 schematically shows memory banks #0-#3 and a column decode circuit 2a. 
Memory banks #0-#3 are similar in configuration and memory bank#0 will be described representatively.
Memory bank#0 includes memory blocks M0-M3 (memory banks #1-#3 include memory blocks M4-M15) and sense amplifier bands SAG#0a to SAG#0e (hereinafter generally referred to as a sense amplifier band SAG#0) and memory cell arrays 10-13 are each arranged between two of sense amplifier bands SAG#0a to SAG#0e. Column decode circuit 2a includes a column predecode circuit 300, a block select line BS less than 15:0 greater than  corresponding to each of memory blocks M0-M15, hereinafter generally referred to as a block select line BS), a bank select line SBA less than 3:0 greater than  corresponding to each of memory banks #0-#3, hereinafter generally referred to as a bank select line SBA), column select lines CSLER less than 3:0 greater than  and CSLOR less than 3:0 greater than  shared by all memory banks and dedicated to reading data, (hereinafter generally referred to as column select lines CSLER and CSLOR), column select lines CSLEW less than 3:0 greater than  and CSLOW less than 3:0 greater than  shared by all memory banks and dedicated to writing data (hereinafter generally referred to as column select lines CSLEW and CSLOW), CSL decode circuits 100a-100e (hereinafter generally referred to as a CSL decode circuit 100), and block select latch circuits 200a-200d (hereinafter generally referred to as a block select latch circuit 200). While herein column select lines CSLER and CSLOR or column select lines CSLEW and CSLOW are adapted to have an 8-bit configuration, they are not limited thereto and may be of n1 bit equal to or grater than eight bits, wherein n1 represents a natural number.
FIG. 29 shows circuit configurations of column predecode circuit 300.
In FIG. 29(A) a column address NCA less than 2:0 greater than  is a signal representing a column address CA less than 2:0 greater than  that is inverted by an inverter INV.
FIG. 29(B) shows a timing generation circuit GT receiving clock signals Read. CLK and Write. CLK exclusively for read and write operations to generate timing signals RTM and WTM, respectively.
FIG. 29(C) shows a data reading logic unit generating a signal selecting any one of column select lines CSLER0-CSLER3 and CSLOR0-CSLOR3. While herein a column select line is selected for reading data, also for writing data, timing signal WTM for the write operation is received and one of writing column select lines CSLEW less than 3:0 greater than  and CSLOW less than 3:0 greater than  is selected.
AND circuit 301 receives column addresses NCA(0)-NCA(2) input, performs a logical operation thereon and outputs the result of the operation to an AND circuit 302 and AND circuit 302 receives timing signal RTM and an output of AND circuit 301, performs a logical operation thereon and transmits the result of the operation to column select line CSLER0. An AND circuit 303 receives column addresses NCA(0), CA(1) and NCA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 304, and AND circuit 304 receives timing signal RTM and an output of AND circuit 303, performs a logical operation thereon and transmits the result of the operation to column select line CSLER1. An AND circuit 305 receives column addresses NCA(0), NCA(1) and CA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 306, and AND circuit 306 receives timing signal RTM and an output of AND circuit 305, performs a logical operation thereon and transmits the result of the operation to column select line CSLER2. An AND circuit 307 receives column addresses NCA(0), CA(1) and CA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 308, and AND circuit 308 receives timing signal RTM and an output of AND circuit 307, performs a logical operation thereon and transmits the result of the operation to column select line CSLER 3.
An AND circuit 309 receives column addresses CA(0), NCA(1) and NCA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 310, and AND circuit 310 receives timing signal RTM and an output of AND circuit 309, performs a logical operation thereon and transmits the result of the operation to column select line CSLOR0. An AND circuit 311 receives column addresses CA(0), CA(1) and NCA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 312, and AND circuit 312 receives timing signal RTM and an output of AND circuit 311, performs a logical operation thereon and transmits the result of the operation to column select line CSLOR1. An AND circuit 313 receives column addresses CA(0), NCA(1), CA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 314, and AND circuit 314 receives timing signal RTM and an output of AND circuit 313, performs a logical operation thereon and transmits the result of the operation to column select line CSLOR2. An AND circuit 315 receives column addresses CA(0), CA(1), CA(2), performs a logical operation thereon and outputs the result of the operation to an AND circuit 316, and AND circuit 316 receives timing signal RTM and an output of AND circuit 315, performs a logical operation thereon and transmits the result of the operation to column select line CSLOR3.
For example, if timing signal RTM have a high level and column addresses NCA(0)-NCA(2) all have a high level, column select line CSLER0 is activated and thus attains a high level and a column is selected to read data.
FIG. 30 shows a circuit configuration of a block select latch circuit 200a. 
Although herein block select latch circuit 200a alone will be described, other block select latch circuits 200b-200e have a similar circuit configuration and thus will not be described specifically.
Block select latch circuit 200a includes a latch circuit LAT and drivers 201 and 202.
Latch circuit LAT receives a signal on block select line BS0 and timing signal RTM (WTM), latches the signal on block select line BS0, and uses drivers 201 and 202 to generate latch control signals XL0 and YL0, respectively. For example, latch circuit LAT operates in response to timing signal RTM (WTM) of a high level to latch the signal on block select line BS0 and output it to CSL decode circuit 100.
FIG. 31 shows a circuit configuration of CSL decode circuit 100b connected to an odd-numbered sense amplifier band SAG#0b. 
CSL decode circuit 100b is connected to an odd-numbered sense amplifier band SAG#0b, and receives signals on column select lines CSLEW less than 3:0 greater than  and CSLER less than 3:0 greater than , latch control signals YL1 and XL0 and a signal on bank select line SAB0 to generate a column select signal CLEW less than 3:0 greater than  used to select a column to write data and a column select signal CLER less than 3:0 greater than  used to select a column to read data (hereinafter generally referred to as column select signals CLEW and CLER).
CSL decode circuit 100b includes a logic circuit 106, inverters 101-103 and NAND circuits 104 and 105.
Logic circuit 106 includes AND circuits 108 and 109 and an NOR circuit 107. AND circuit 108 receives latch control signal YL1 and a signal on bank select line SBA0, performs a logical operation thereon and outputs the result of the operation to NOR circuit 107. AND circuit 109 receives latch control signal XL0 and the signal on bank select line SBA0, performs a logical operation thereon and outputs the result of the operation to NOR circuit 107. NOR circuit 107 receives the outputs of AND circuits 108 and 109, performs a logical operation thereon and outputs the result of the operation. Inverter 103 receives the signal from logic circuit 106, inverts the signal and outputs the inverted signal to NAND circuits 104 and 105. NAND circuit 104 is connected to column select line CSLEW less than 3:0 greater than  and inverter 103 to receive signals from the column select line and the inverter, performs a logical operation thereon and outputs the result of the operation to inverter 101. Inverter 101 receives a signal from NAND circuit 104 and inverts the signal to generate column select signal CLEW less than 3:0 greater than , NAND circuit 105 is connected to column select line CSLER less than 3:0 greater than  and inverter 103 to receive signals from the column select line and the inverter, performs a logical operation thereon and outputs the result of the operation to inverter 102. Inverter 102 receives the signal from NAND circuit 105 and inverts the signal to generate column select signal CLER less than 3:0 greater than .
For example, if latch control signals YL1 and XL0 both have a high level and bank select line SBA0 also has a high level, AND circuits 108 and 109 both attain a high level. Accordingly, NOR circuit 107 outputs a signal having a low level and thus via inverter 103 NAND circuits 104 and 105 each receive a signal having a high level. Thus if of column select line CSLEW less than 3:0 greater than  column select line CSLEW0 transmits a signal having a high level then column select signal CLEW0 attains a high level and if of CSLER less than 3:0 greater than  column select line CSLER0 transmits a signal having a high level then column select signal CLER0 attains a high level. In response to such column select signals sense amplifier band SAG#0b allows a column to be selected to read/write data.
While herein CSL decode circuit 100b is described, CSL decode circuit 100d has a similar configuration and it thus will not be described specifically.
FIG. 32 shows a circuit configuration of CSL decode circuit 100c connected to an even-numbered sense amplifier band SAG#0c, operative in response to signals on column select lines CSLOW less than 3:0 greater than  and CSLOR less than 3:0 greater than  to generate column select signals CLOW less than 3:0 greater than  and CLOR less than 3:0 greater than , respectively. It has a circuit connection similar to that of CSL decode circuit 100b and thus will not be described specifically.
CSL decode circuits 100a and 100e are different from CSL decode circuit 100c in that in the former a latch control signal input is a signal input. More specifically, for CSL decode circuit 100a, latch control signal XL1 input to NAND circuit 109 is replaced with a ground voltage GND (of a low level) for input. For CSL decode circuit 100e, latch control signal YL2 input to NAND circuit 108 is replaced with ground voltage GND (of the low level) for input. The reminder is similar to that of CSL decode circuit 100c and thus will not be described specifically.
FIG. 33 shows a relationship of bit line pair BL, /BL for sense amplifier bands SAG#0b and SAG#0c arranged on opposite sides of memory block M1.
Herein sense amplifier band SAG#0 is provided in a shared SA system.
Memory block M1 includes bit line pairs BL0, /BL0 to BL7, /BL7. Sense amplifier band SAG#0b includes sense amplifier control circuits SAC0-SAC3 (hereinafter generally referred to as a sense amplifier control circuit SAC) each corresponding to an even-numbered bit line pair BL, /BL, and sense amplifier band SAG#0c includes sense amplifier control circuit SAC arranged to correspond to an odd-numbered bit line pair BL, /BL, respectively. Furthermore each sense amplifier control circuit SAC is connected to an input/output line pair GIOR0, /GIOR0.
Sense amplifier control circuits SAC0-SAC3 receive column select signals CLER0-CLER3, respectively, and sense amplifier band SAG#0c receive column select signals CLOR0-CLOR3 corresponding to respective bit line pairs BL, /BL. While herein column select signals are only shown for a read operation, they are also applicable to a write operation and corresponding to column select signal CLER less than 3:0 greater than  column select signal CLEW less than 3:0 greater than  is input for the write operation and corresponding to column select signal CLOR less than 3:0 greater than  column select signal CLOW less than 3:0 greater than  is input for the write operation. Herein if bit line pair BL0, /BL0 is selected, column select signal CLER0 (of a high level) is input to read data. If bit line pair BL2, /BL2 is selected, column select signal CLER1 (of the high level) is input to read data.
FIG. 34 shows a circuit configuration of sense amplifier band SAG#0b performing a column select operation.
Sense amplifier band SAG#0b includes sense amplifier control circuits SAC0-SAC3 connected to a writing input/output line pair GIOW0 and /GIOW0 and a reading input/output line pair GIOR0 and /GIOR0 connected to a data input/output circuit communicating data.
Sense amplifier control circuit SAC0 will now be described. The other sense amplifier control circuits SACs have a similar circuit configuration and thus will not be described specifically.
Sense amplifier control circuit SAC0. includes N channel MOS transistors NL0 and /NL0, QW0 and/QW0, QRB0 and/QRB0, QRC0 and /QRC0, NR0 and /NR0, an equalizer EQ0, and a sense amplifier SA0.
N channel M0S transistors NL0 and /NL0, and NR0 and /NR0 are arranged as gate circuits for bit line pair BL0, /BL0 for memory blocks M0 and M1 respectively and turn on in response to gate select signals SHRL and SARR to select one of the gate circuits. Equalizer EQ0 is activated in response to an activation signal BLEQ to precharge bit line pair BL0, /BL0 connected to sense amplifier SA0 to transmit a data signal. Sense amplifier SA0 is activated in response to sense amplifier activation signals SE and /SE to amplify a signal received on bit line pair BL0, /BL0. N channel M0S transistors QW0 and /QW0 is a gate circuit electrically coupling bit line pair BL0, /BL0 and input/output line pair /GIOW0, GIOW0 together, respectively.
A write operation will now be described.
When column select signal CLEW0 attains a high level, N channel M0S transistors QW0 and /QW0 turn on and data on input/output line pair /GIOW0, GIOW0 is transmitted via sense amplifier SA0 to bit line pair BL0, /BL0, respectively, to write data.
A read operation will now be described.
N channel M0S transistors QRB0 and QRC0 are connected in series between input/output line /GIOR0 and a node N0 connected to ground voltage GND. N channel M0S transistors /QRB0 and /QRC0 are arranged in series between input/output line GIOR0 and node N0 connected to ground voltage GND. Furthermore, N channel M0S transistors QRB0, /QRB0 have their respective gates electrically connected to bit line pair BL0, /BL0, respectively, and N channel M0S transistors QRC0, /QRC0 have their respective gates both receiving column select signal CLER0.
When column select signal CLER0 attains a high level, N channel M0S transistors QRC0 and /QRC0 turn on. Then data on bit line pair BL0, /BL0 are transmitted to input/output line pair /GIOR0, GIOR0 to read data. When sense amplifier SA0 provides amplification, one of NMOS transistors QRB0 and /QRB0 turns on, and node N0 connected to ground voltage GND and one of input/output line pair GIOR0 and /GIOR0 are electrically connected to read data.
Similarly, when column select signal CLEW3 attains a high level, sense amplifier control circuit SAC3 is activated, and via sense amplifier SA3 and equalizer EQ3 bit line pair BL6, /BL6 receive data on input/output line pair /GIOW0, GIOW0, respectively, to write data. When column select signal CLER3 attains the high level, sense amplifier control circuit SAC3 is activated and data on bit line pair BL6, /BL6 are read onto input/output line pair /GIOW0, GIOW0. Other sense amplifier control circuits SAC1 and SAC2 similarly operate and thus will not be described specifically.
Again with reference to FIG. 28, the FIG. 28 memory cell array is configured of four memory banks #s each having four memory blocks. Each memory block and sense amplifier band SAG# have a relationship in the shared SA system as has been described previously.
Herein, although not shown in the figure, each memory bank has a connection, each with two sense amplifier bands SAG#s arranged, for example so that while memory bank#0 is activated, sense amplifier band SAG# of memory bank#1 can be activated simultaneously.
Thus for a single memory bank# the number of sense amplifier bands SAG#s is constantly equal to that of memory blocks plus one.
Sense amplifier band SAG# and bit line pair BL, /BL have a relationship therebetween, as follows: for memory bank#0, odd-numbered sense amplifier bands SAG#0b and SAG#0d receive a signal on column select lines CSLER less than 3:0 greater than  and CSLEW less than 3:0 greater than  selecting an even-numbered bit line pair, and even-numbered sense amplifier bands SAG#0a, SAG#0c and SAG#0e receive a signal on column select lines CSLOR less than 3:0 greater than  and CSLOW less than 3:0 greater than  selecting an odd-numbered bit line pair.
However, column select lines CSLER less than 3:0 greater than  and CSLEW less than 3:0 greater than  selecting an even-numbered bit line pair are responsible for a number of sense amplifier bands SAG#0 and column select lines CSLOR less than 3:0 greater than  and CSLOW less than 3:0 greater than  selecting an odd-numbered bit line pair are responsible for a different number of sense amplifier bands SAG#0, and accordingly there is introduced a difference in load of two to three per memory bank#. For a 4-memory bank# configuration there would be introduced a difference in load of 8:12. Thus a column select signal is transmitted at a different timing disadvantageously to prevent a rapid operation of a column cycle.
The present invention has been made to overcome the disadvantage described above and it contemplates reducing a difference in timing associated with that in load, and thus providing a faster column-related operation.
The present invention provides a semiconductor memory device including: first and second memory banks each including M memory blocks each divided into first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands each inputting and outputting data to and from one of the first and second memory regions in at least one, adjacent memory block of the M memory blocks, the M memory blocks being each arranged between adjacent two of the (M+1) sense amplifier bands; a first select line activated when the first memory region is selected; and a second select line activated when the second memory region is selected, the first memory bank having odd-numbered ones of the (M+1) sense amplifier bands each coupled with the first select line to input and output the data to and from the first memory region, and even-numbered ones of the (M+1) sense amplifier bands each coupled with the second select line to input and output the data to and from the second memory region, the second memory bank having odd-numbered ones of the (M+1) sense amplifier bands each coupled with the second select line to input and output the data to and from the second memory region, and even-numbered ones of the (M+1) sense amplifier bands each coupled with the first select line to input and output the data to and from the first memory region.
Thus in the present semiconductor memory device the first select line is responsible for activating in the first and second memory banks odd-and even-numbered sense amplifier bands, respectively, of (M+1) sense amplifier bands arranged on opposite sides of M memory blocks including in each of the first and second memory banks and the second select line is responsible for activating in the first and second memory banks even- and odd-numbered sense amplifier bands, respectively, of the (+1) sense amplifier bands to allow the first and second select lines to be uniform in load and thus eliminate a difference in timing between the first and second select lines to provide a faster column-related operation.
Preferably, the M memory blocks each having a plurality of memory cells arranged in rows and columns to hold data, a plurality of bit lines provided to correspond to the rows of the memory cells, respectively, and a plurality of word lines provided to correspond to the columns of the memory cells, respectively, the semiconductor memory device further comprising an input/output line arranged parallel to the plurality of bit lines and connected to each of the (M+1) sense amplifier bands, wherein the first and second select lines traverse the plurality of bit lines.
In the present semiconductor device an input/output line can be arranged parallel to a bit line and a select line can be arranged to traverse the bit line to reduce a layout area.
Preferably the semiconductor memory device further includes a column select circuit connected to the first and second select lines, wherein the first and second select lines transmit a decoded select signal from the column select circuit.
The present invention provides a semiconductor device including: a plurality of memory banks each including M memory blocks each having a plurality of memory cells in rows and columns and divided into first and second memory blocks having an equal number of columns of memory cells, M representing an even number of no less than two, each the memory bank also including (M+1) sense amplifier bands each inputting and outputting data to and from one of the first and second memory regions in at least one adjacent memory block of the M memory blocks, the M blocks being each arranged between adjacent two of the (M+1) sense amplifier bands, the plurality of memory banks each having odd-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the first memory region, and even-numbered ones of the (M+1) sense amplifier bands inputting and outputting the data to and from second memory region; a predecode circuit generating a first select signal selecting one of the first and second memory regions and a second select signal selecting a column of memory cells in each of the first and second memory regions; a column select signal line transmitting the second select signal; and (M+1) decode circuits arranged to correspond to the (M+1) sense amplifier bands, respectively, in each of the plurality of memory banks, each operative in response to the first and second select signals to select one of the corresponding columns of memory cells, the (M+1) decode circuit being each as connected to the column select signal line.
Preferably the semiconductor memory device further includes a first select line transmitting the first select signal, wherein the (M+1) decode circuits are each further connected to the first select line.
In the present semiconductor device there are provided a column select signal line selecting a column of a memory block, and a first select line transmitting a first select signal selecting one of the first and second memory regions, connected to (M+1) sense amplifier bands arranged on opposite sides of M memory blocks included in each of a plurality of memory banks, to provide a uniform load and hence a faster column-related operation.
In particular, the first select line includes a first region select line transmitting a first region select signal and a second region select line transmitting a second region select signal, the first and second region select signals selecting the first and second memory regions, respectively, and the odd-numbered ones of the (X+1) decode circuits are each connected to the first region select line, and the even-numbered ones of the (M+1) decode circuits are each connected to the second region select line.
In the present semiconductor memory device the first select line includes a first region select line selecting a first region and a second region select line selecting a second region and can connect each odd-numbered one of the (M+1) decode circuits and the first region select line together and connect each even-numbered one of the (M+1) decode circuits and the second region select line together to achieve a uniform load to provide a faster column-related operation.
Preferably, the semiconductor device further includes a first select line transmitting the first select signal, wherein: the column select signal line includes a plurality of subordinate column select signal lines corresponding to the plurality of memory banks respectively; and the (M+1) decode circuits are each connected to a corresponding one of the plurality of subordinate column select signal lines and further to the first select line.
In the present semiconductor memory device a plurality of memory banks each include M memory blocks sandwiched by (M+1) sense amplifier bands connected to a subordinate column select signal line selecting a column of a memory block that is provided to correspond to each memory bank to reduce a load and thus achieve a further faster, column-related operation.
In particular, the first select line includes a first region select line transmitting a first region select signal and a second region select line transmitting a second region select signal, the first and second region select signals selecting the first and second memory regions, respectively, and the odd-numbered ones of the (M+1) decode circuits are each connected to the first region select line and the even-numbered ones of the (M+1) decode circuits are each connected to the second region select line.
In the present semiconductor device, first and second region select lines can be provided to select first and second regions, respectively, of a memory block and of (M+1) decode circuits an odd-numbered decode circuit and the first region select line can be connected together and an odd-numbered decode circuit and the second region select line can be connected together to achieve a uniform load and thus provide a faster column-related operation.
The present invention provides a semiconductor memory device including: a plurality of memory banks each including M memory blocks each having a plurality of memory cells in rows and columns and a plurality of bit line provided to respectively correspond to the columns of the memory cells, M representing an even number of no less than two, the M memory blocks being each divided into first and second memory regions each having an equal number of the columns of the memory cells, the plurality of memory banks each further including (M+1) sense amplifier bands each inputting and outputting data to and from one of the first and second memory regions in at least one, adjacent memory block of the M memory blocks, the M blocks being each arranged between adjacent two of the (M+1) sense amplifier bands, the plurality of memory banks each having odd-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the first memory region and even-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the second memory region; a plurality of first decode circuits arranged to correspond to the odd-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a plurality of second decode circuits arranged to correspond to the even-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a plurality of first select lines provided to correspond to the plurality of first decode circuits, respectively, and each transmitting a first select signal to effect the column select operation in the first memory region corresponding thereto; and a plurality of second select lines provided to correspond to the plurality of second decode circuits, respectively, and each transmitting a second select signal to effect a column select operation in the second memory region corresponding thereto.
In the present semiconductor device a first select line selecting a column of an odd-numbered sense amplifier band of a memory block and a second select line selecting a column of an even-numbered sense amplifier band of a memory block can be connected to each sense amplifier band for each memory block of each memory bank to provide a uniform load and reduce a difference in timing between the first and second select lines and also to reduce a load to provide a faster, column-related operation.
The present invention provides a semiconductor memory device including: a plurality of memory banks each including M memory blocks each having a plurality of memory cells in rows and columns and a plurality of bit line provided to respectively correspond to the columns of the memory cells, M representing an even number of no. less than two, the M memory blocks being each divided into first and second memory regions each having an equal number of the columns of the memory cells, the plurality of memory banks each further including (M+1) sense amplifier bands each inputting and outputting data to and from one of the first and second memory regions in at least one, adjacent memory block of the M memory blocks, the M blocks being each arranged between adjacent two of the M+1) sense amplifier bands, the plurality of memory banks each having odd-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the first memory region and even-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the second memory region; a plurality of first decode circuits arranged to correspond to the odd-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a plurality of second decode circuits arranged to correspond to the even-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a first select line connected to each the first decode circuit to transmit a first select signal to effect the column select operation in the first memory region; a second select line connected to each the second decode circuit to transmit a second select signal to effect the column select operation in the second memory region; and a delay load circuit provided for one of the first and second select lines to delay signal propagation on one of the first and second select lines for a predetermined period of time.
In the present semiconductor memory device a first select line selecting a column of an odd-numbered sense amplifier band of a memory block and a second select line selecting a column of an even-numbered sense amplifier band of a memory block can be shared by each memory bank and connected to their respective sense amplifier bands and one of the first and second select lines can be connected to a delay load circuit to allow the first and second select lines to be uniform in load and eliminate a difference in timing between the first and second select lines to achieve a faster, column-related operation.
Preferably the delay load circuit has one of an inverter and an NAND circuit.
In the present semiconductor memory device the delay load circuit can be configured by an inverter or a NAND circuit and it can thus be simplified in configuration.
The present invention provides a semiconductor memory device including: a plurality of memory banks each including M memory blocks each having a plurality of memory cells in rows and columns and a plurality of bit line provided to respectively correspond to the columns of the memory cells, M representing an even number of no less than two, the M memory blocks being each divided into first and second memory regions each having an equal number of the columns of the memory cells, the plurality of memory banks each further including (M+1) sense amplifier bands each inputting and outputting data to and from one of the first and second memory regions in at least one, adjacent memory block of the M memory blocks, the M blocks being each arranged between adjacent two of the (+1) sense amplifier bands, the plurality of memory banks each having odd-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the first memory region and even-numbered ones of the (M+1) sense amplifier bands each inputting and outputting the data to and from the second memory region; a plurality of first decode circuits arranged to correspond to the odd-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a plurality of second decode circuits arranged to correspond to the even-numbered sense amplifier bands, respectively, and each operative to effect a column select operation; a first local select line connected to each the first decode circuit to transmit a first select signal to effect the column select operation in the first memory region; a second local select line connected to each the second decode circuit to transmit a second select signal to effect the column select operation in the second memory region; a first main select line shared by the plurality of memory banks and transmitting the first select signal; a second main select line shared by the plurality of memory banks and transmitting the second select signal; a first signal transmission transmitting the first select signal from the first main select line to the first local select line; and a second signal transmission transmitting the second select signal from the second main select line to the second local select line.
In the present semiconductor memory device, memory banks shares a first main select line, a second main select line, a first local select line transmitting a first select signal from the first main select line and a second local select line transmitting a second select signal from the second main select line and the first and second local select lines and each memory bank""s odd- and even-numbered decode circuits can respectively be connected together to eliminate a difference in timing between the first and second local select lines and thus provide a faster, column-related operation.
Preferably, the first local select line includes a plurality of first subordinate local select lines corresponding to each of the plurality of memory banks, second local select line includes a plurality of second subordinate local select lines corresponding to each of the plurality of memory banks, and in each of the plurality of memory banks, each the first decode circuit is connected to a corresponding one of the plurality of first subordinate local select lines and each the second decode circuit is connected to a corresponding one of the plurality of second subordinate local select lines.
In the present semiconductor memory device a first local select line can include a plurality of first subordinate local select lines and a second local select line can include a plurality of second subordinate local select lines, and the first decode circuit in each memory bank and a corresponding first subordinate local select line can be connected together and the second decode circuit in each memory bank and a corresponding second subordinate local select line can be connected together to eliminate a difference in timing between the first and second subordinate local select lines and thus provide a faster, column-related operation.